Manufacturing a silicon chip is a complex process that requires many precisely controlled steps. Typically, the design flow for manufacturing the chip includes logical synthesis, timing analysis, place and route, and verification. Out of these steps, verification is generally the most resource and time intensive step in the design flow. A computer system performs the verification by running various simulations to test the design of chip. These simulations can include functional verification, timing verification, and physical verification.
In order to simulate a design, a source language specification is compiled and elaborated to create a run-time representation of the chip in memory. The computer system initializes a memory model and performs a reset sequence before the test vector drives the model into a unique path. The verification process may include many test vectors, which each perform the reset sequence. This process is both memory intensive and time consuming. For example, in total, the verification process can take upwards of 70% of the entire design cycle as each simulation takes a large amount of time to run partly due to having to generate the in-memory representation of the chip for each test vector. As technology improves and chip designs increase in complexity, the simulations will increase in number and complexity thereby making the verification step a larger bottleneck in the design flow.